Abstract
This paper presents a novel design to develop parallel pipelined architectures for the fast Fourier
transform (FFT). The architecture is based on the radix-4 algorithm. By exploiting the regularity of the
algorithm, butterfly operation and multiplier modules were designed. The architecture adopts four
butterflies, and the pipeline stage is optimized to balance the processing speed and the area. Novel parallel
pipelined architectures for the computation of complex and real valued fast Fourier transform are derived