A Novel High Performance Enhanced Pulse Triggered Flip Flop

In This paper, a novel high performance pulse Triggered flip- flop design is presented. The proposed design reduces the number of transistors stacked in the discharging path and also reduces the overall switching delay. A conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. The proposed EPTL avoids unnecessary internal node transitions to improve the power consumption as compared to previously circuit. We also design 16-bit Shift Resistor using proposed EPTL. The proposed design features the best power consumption and power-delay-product performance as compared to the other three previously designed FF’s. Its maximum power saving compared to the conventional P-FF designs is up to 20% and 16bit shift resistor has 39% power saving compared to previous EPTL based Shift register