Design and analysis of self clocked flip-flop based shift registers using 90 nm CMOS technology

This paper enumerates the efficient design and analysis of 4 bit shift registers using self clocked D flip-flop as a storage element. Self clocked flip-flop utilize internal clock generation mechanism, due to this it doesn’t require external clock synchronization. It is designed by utilizing relatively less number of transistors than conventional designs, which results in drastic improvement of power performance, package density and speed. Here self triggered D flip-flop is used in order to design Serial In Serial Out(SISO), Serial In Parallel Out(SIPO), Parallel In Serial Out(PISO) and Parallel In Parallel Out(PIPO) shift registers. The shift registers presented here requires comparatively less die area, reduced power consumption and high speed than conventional shift registers. Design and simulation of shift registers have been carried out using Microwind design and simulation tool using 90nm CMOS process.